Integrated circuit chip level secure hardware system using physical attack protection techniques, has protection schemes provided in vertical unification of systems, circuits and packaging technologies and design principles of on-chip monitoring circuits for sensing attackers attempts
	GANESAN V; HEMALATHA B; BALAJI S; VINUDEVI G; VANITHAMANI P; YOUNIS S; YOGESHWARAN A
	2023-10-16
专利权人	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
申请日期	2023-10-16
专利号	IN202341069493-A
成果简介	NOVELTY - The system has integrated circuit (IC) chips in a practical utilization environment. Overviews of physical attacks are provided on cryptographic circuits associated vulnerabilities in an IC chip. Protection schemes are provided in a vertical unification of systems, circuits, and packaging technologies. The design principles of on-chip monitoring circuits sense the attackers attempts and are tested with silicon demonstrators. Physical structures are explored for secure IC chips to establish protections against multimodal side-channel attacks. Backside buried metal (BBM) wirings in a silicon substrate are unified with front side complementary metal-oxide semiconductor (CMOS) circuits. USE - IC chip level secure hardware system using physical attack protection techniques. ADVANTAGE - The system achieves avoidance, detection and resiliency against electromagnetic and laser attacks.
IPC 分类号	G06F-021/55 ; G06F-021/57 ; G06F-021/72 ; H01L-027/092 ; H04L-009/00
国家	印度
专业领域	信息技术
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/19883
专题	中国科学院新疆生态与地理研究所
作者单位	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
推荐引用方式 GB/T 7714	GANESAN V,HEMALATHA B,BALAJI S,et al. Integrated circuit chip level secure hardware system using physical attack protection techniques, has protection schemes provided in vertical unification of systems, circuits and packaging technologies and design principles of on-chip monitoring circuits for sensing attackers attempts. IN202341069493-A[P]. 2023.

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