Double tail architecture for analysis of delay and power of the dynamic comparator of flash analog to digital comparators (ADCs), has two tail transistors, where pre-amplifier design determines offset voltage and latch determines speed of comparator
	GANESAN V; PRATHIBA T; PEARLY B; JEEVA J; DARSHAN B; SIVA M
	2023-10-16
专利权人	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
申请日期	2023-10-16
专利号	IN202341069712-A
成果简介	NOVELTY - The double tail architecture has two tail transistors. Dynamic comparators are superior to static counterpart because of positive feedback which increases latching speed and lower static power consumption. The CMOS(Complementary Metal-Oxide-Semiconductor) dynamic comparator has two parts pre-amplifier and dynamic latch respectively. The pre-amplifier design determines offset voltage and latch determines the speed of comparator. . The common mode voltage is applied at the input to operate input transistors in saturation which helps in increasing the speed but variation of common mode input voltage results in variability in delay significantly which makes the circuit not suitable for high speed operations. USE - Double tail architecture for analysis of delay and power of the dynamic comparator of flash analog to digital comparators (ADCs). ADVANTAGE - The comparator can be designed with high precision, low voltage, high dynamic range, lower power dissipation, high speed, robust and less offset voltage. The comparators are superior to static counterpart because of positive feedback which increases latching speed and lower static power consumption. The pre-amplifier design determines offset voltage and latch determines the speed of comparator. If offset voltage is reduced, it directly helps in improving precision. The common mode voltage is applied at the input to operate input transistors in saturation which helps in increasing the speed but variation of common mode input voltage results in variability in delay significantly which makes the circuit not suitable for high speed operations. The power consumption can be reduced by 46% and area can also be optimized by 38.63% if circuit is designed efficiently.
IPC 分类号	G06F-030/398 ; H03M-001/00 ; H03M-001/12 ; H03M-001/36 ; H04W-004/38
国家	印度
专业领域	信息技术
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/19881
专题	中国科学院新疆生态与地理研究所
作者单位	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
推荐引用方式 GB/T 7714	GANESAN V,PRATHIBA T,PEARLY B,et al. Double tail architecture for analysis of delay and power of the dynamic comparator of flash analog to digital comparators (ADCs), has two tail transistors, where pre-amplifier design determines offset voltage and latch determines speed of comparator. IN202341069712-A[P]. 2023.

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