Multiplier circuit design for performance of processor depends on multiplier on multiplication process based on add and shift algorithm, has partial product that is generated by multiplication of multiplicand with multiplier bit
	HABIBA U H; SAHIB K A S K A; ARULSELVI S; LIKHYATH K M; RAJU K; HARISH A; REDDY K V D
	2023-10-16
专利权人	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
申请日期	2023-10-16
专利号	IN202341069959-A
成果简介	NOVELTY - The multiplier circuit design has a partial product that is generated by the multiplication of the multiplicand with a multiplier bit. The partial product is shifted according to their bit orders and then added. The addition is performed with normal carry propagate adder. The N-1 adders are required, where N is the multiplier length. Multiplier architecture consists of three stages. A partial product generation stage is generated by AND operation. The partial product addition stage carried by different adders and final addition stage. The speed of the multiplier depends upon partial product addition stage. USE - Multiplier circuit design for performance of a processor depends on the multiplier depends on the multiplication process based on add and shift algorithm using application, such as Very-large-scale integration (VLSI), digital signal processing, deep learning, and artificial intelligence. ADVANTAGE - The multiplier circuit design requires high performing processors to obtain the processing of huge amount of data, the multipliers are computation of partial products and then the summation of partial products.
IPC 分类号	A61K-009/00 ; G06F-017/10 ; G06F-007/48 ; G06F-007/53 ; G06F-007/533
国家	印度
专业领域	信息技术
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/19870
专题	中国科学院新疆生态与地理研究所
作者单位	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
推荐引用方式 GB/T 7714	HABIBA U H,SAHIB K A S K A,ARULSELVI S,et al. Multiplier circuit design for performance of processor depends on multiplier on multiplication process based on add and shift algorithm, has partial product that is generated by multiplication of multiplicand with multiplier bit. IN202341069959-A[P]. 2023.

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