Performance modelling system for convolutional neural inference accelerators on field programmable digital array, has field programmable gate array accelerator comprising vector generator module for matching index between sparse
	KALAISELVI B; UMAMAHESHWARI M; SUBBULAKSHMI S; VANITHAMANI P; BHARATH K; KUMAR S M K; SAI V G; ACHARI P K
	2023-10-16
专利权人	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
申请日期	2023-10-16
专利号	IN202341069429-A
成果简介	NOVELTY - The system has sparse wise data flow which is used to skip the cycles of processing multiply-and-accumulates (MACs) with zero weights and exploit data statistics to reduce energy through zeros gating to avoid unnecessary computations. The sparse wise data flow leads to a low bandwidth requirement and high data sharing. A field programmable gate array (FPGA) accelerator comprises a vector generator module (VGM) which matches the index between sparse. USE - Performance modelling system for convolutional neural inference accelerators on field programmable digital array. ADVANTAGE - The system is efficient and easy to use, reduces computational and data cost of on-chip storage and off-chip bandwidth in accelerator architecture design and achieves low bandwidth requirement and high data sharing.
IPC 分类号	G06K-009/62 ; G06N-003/04 ; G06N-003/063 ; G06N-003/08 ; H04W-016/14
国家	印度
专业领域	信息技术
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/19839
专题	中国科学院新疆生态与地理研究所
作者单位	BHARATH HIGHER EDUCATION & RES INST (BHAR-Non-standard)
推荐引用方式 GB/T 7714	KALAISELVI B,UMAMAHESHWARI M,SUBBULAKSHMI S,et al. Performance modelling system for convolutional neural inference accelerators on field programmable digital array, has field programmable gate array accelerator comprising vector generator module for matching index between sparse. IN202341069429-A[P]. 2023.

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