ARBITRARY MODULUS ACCUMULATING ADDER comprises an n-bit multiplexer, (n+1)-bit adder, n-bit register, first and second information inputs of the device,
	PETRENKO V I; DIBROV N; DIKANSKII D A
	2024-08-01
专利权人	UNIV NORTH CAUCASUS FEDERAL (UYNC-Non-standard)
申请日期	2024-08-01
专利号	RU2835073-C1
成果简介	NOVELTY - Arbitrary modulus accumulating adder comprises an n-bit multiplexer, (n+1)-bit adder, n-bit register, first and second information inputs of the device, information outputs of the device, a clock input of the device, n-bit register synchronization input , device initial state setting input, n-bit register reset input , n full single-bit adders, (n+1)-bit multiplexer, “2AND-NOT” element, “NOT” element, n-input “OR” element. USE - Computer engineering. ADVANTAGE - Reduced volume of used equipment. 1 cl, 1 dwg
IPC 分类号	G06F-007/501 ; G06F-007/72
国家	俄罗斯
专业领域	信息技术
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/15577
专题	中国科学院新疆生态与地理研究所
作者单位	UNIV NORTH CAUCASUS FEDERAL (UYNC-Non-standard)
推荐引用方式 GB/T 7714	PETRENKO V I,DIBROV N,DIKANSKII D A. ARBITRARY MODULUS ACCUMULATING ADDER comprises an n-bit multiplexer, (n+1)-bit adder, n-bit register, first and second information inputs of the device,. RU2835073-C1[P]. 2024.

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