Method for determining electrical equivalent inductance of via end in printed circuit board, involves positioning copper trace at top part of epoxy dielectric, and locating via end at predefined distance from input end of copper trace and connected to ground plane
	BANERJEE D; DHAR P; MAJUMDAR A; GHOSAL A; BANERJEE A
	2024-12-27
专利权人	GURU NANAK TECHNOLOGY INST (GURU-Non-standard)
申请日期	2024-12-27
专利号	IN202431103464-A
成果简介	NOVELTY - The method involves providing a printed circuit board (PCB) (104) provided with an epoxy dielectric (106), where the epoxy dielectric is a glass reinforced-epoxy dielectric. A copper trace (108) is positioned at a top part of the epoxy dielectric above a ground plane at a predefined height. A via end (102) is located at a predefined distance from an input end of the copper trace and connected to a ground plane, where an electrical equivalent inductance of the via end is determined based on a curve fitting technique with log functions in linear regression technique to generate a modified empirical formula. USE - Method for determining electrical equivalent inductance of a via end i.e. thin cylindrical post, in a PCB, for using a high-frequency structure simulator (HFSS). ADVANTAGE - The method enables reducing computational complexity and enabling more straightforward integration into the PCB design tools by eliminating image considerations. The method enables ensuring that the electrical and physical characteristics of the PCB are consistent, thus allowing for precise modeling of the via inductance. The inductance of vias in a PCB is calculated in a quick and cost-effective addressing the challenges faced by small manufacturers. The method enables offering a reliable and efficient solution for modern PCB design challenges by leveraging advanced mathematical techniques and simplifying traditional approaches, so that the independence from image considerations, combined with the use of industry-standard materials and configurations, thus ensuring wide applicability and adaptability to evolving technological demands. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a system for determining electrical equivalent inductance of a via end in a PCB. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional perspective view of a system for determining electrical equivalent inductance of a via end in a PCB. 100System for determining electrical equivalent inductance of via end in PCB 104PCB
IPC 分类号	G06F-030/39 ; H01Q-001/38 ; H05K-001/02 ; H05K-001/11 ; H05K-003/42
国家	印度
专业领域	材料科学
语种	英语
成果类型	专利
文献类型	科技成果
条目标识符	http://119.78.100.226:8889/handle/3KE4DYBR/13780
专题	中国科学院新疆生态与地理研究所
作者单位	GURU NANAK TECHNOLOGY INST (GURU-Non-standard)
推荐引用方式 GB/T 7714	BANERJEE D,DHAR P,MAJUMDAR A,et al. Method for determining electrical equivalent inductance of via end in printed circuit board, involves positioning copper trace at top part of epoxy dielectric, and locating via end at predefined distance from input end of copper trace and connected to ground plane. IN202431103464-A[P]. 2024.

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